The page was down when I attempted to get the link for you. At the bottom of this page there is a link for Support, and from there a link to Contact Support. For more complete information about compiler optimizations, see our Optimization Notice. Solid State Drives. Thank you very much! Tags: AHCI. All forum topics Previous topic Next topic. Copy link. Barrett, you have in fact the answer in your question. In response to idata. Your P67 chipset is the same as the others, that is correct.
Ok Parsec, I hesitate to start with it. LBA48 is addressing mode used for large capacity drives - more than Gb. The problem was caused by code of determining real drive capacity.
Some drives report their size as 32Gb e. There are special commands for retrieving real capacity and size limit removal. But I didn't know, about their bit clones intended for drives larger than Gb. So, I programmed drives to limit their capacity to Gb wit hold commands : Greate thanks to Alexander Spelicyn aka spelX mail. Saying truth, I reverted it to very old state, when it seemed working. Let's wait for testing result. Experiments show that this workaround helps in many cases. Also, let's wait for results.
Bug-fix in SiS controller detection code. It has very interesting algorithm. There are one or two specific Bridge Device s. This behavior is similar to VIA. But some models need very specific check. Seems to me, this is not too good idea. The problem was because I have lost the line which reverts controller to initial state.
Greate thanks to Mike for testing my buggy versions and supplying me with pretty bug-reports Kb. So, lets try new version Silly bug. As result after successfull UDMA initialization the default code was called and the device not controller! Improved SiS controlelr support. Thanks to Ivano Guerra. Of course, this is beta-version and must be tested.
Try Version 0. Looks like that it is mine. The bug leads to data corruption. So, v29i is removed from the site. Found and fixed bug in Intel IDE support code. It was copied from FBSD 5. Have compared the latest and some old versions and found, than bit value 0x Rewritten Intel IDE controller support code. I hope this will only improve compatibility. Especially for ICH4 , which didn't work with previous version. Ported some new code from FBSD 5. Implemented simplex-mode support.
In this mode IDE channels do not operate simultaneously. For some controllers this mode is inevitable. Such behavior was oberved under latest VMWare release 4. Thanks to Vitaliy for information and testing. Rewritten load balancing code for separate IDE channels and devices connected to single channel.
After that I observed a lot pretty bugs. System worked slowly and randomly crashes. It seemed like sometimes data is not correctly read from HDD. I looked into latest FBSD ata drivers and saw no changes for this controller. At the same time there are bug-reports in formus. I did the same. Unfortunately, I cannot check if it works on that machine. The bug affected on secondary channel's UDMA mode register. Also fixed. Added code for a lot of new controllers. Mostly for SiS and Promese. Paramaters - The most global settings.
See the same place. In general it would be pretty to create configuration utility After that UniATA was successfully added during text-mode w2k setup phase. Note, w2k doesn't support it itself. So, I decided that these setup files are correct now. They worked with Primary channel only. Now UniATA translates virtual addresses to physical itself. This give 2 advantages: 1 No hackar's init methods needed ISA bridged controllers was initialized as PCI and this method worked not on all machines.
On some devices we must wait for DRQ bit assertion if an error occured. Fixed bug with DMA error handling. Previous versions deadly hanged the system if such error occured. Special thanks to Alex Y. INF-file reconstruction is added to distribution. If such controllers are added, they are inserted into. Fixed bug with invisibility of the 2nd IDE channel on onboard controller. W2k doesn't permit such tricks. AdapterControl fuctionality is added.
Tests show, that PnP functionality doesn't work yet under w2k. The main difficulty lays in the following: for PnP support we must create a list of all supported devices in Registry and installation. INF file. It is not compatible with the idea of universal driver.
INF file update will be created. Also probably 2 services using the same uniaata. I've found that problem with onboard controllers was caused by PciIde. Thus a simple installation BAT-file was created. It simply copies UniATA. Now it works under w2k!!! DMA mode check is added before accessing controller registers It doesn't work.
Code for handling some unusual devices Yamaha-CRW those like generating Unexpected Interrupt durring initialization process. They do it a little later than I expected. INF files together with uniata.
Is was found on attempt to play Audio-CD. This bug could also lead to non-oparated state of dual-channel controllers. INF files are moved to Debug and Release directories for corresponding build installation. But you should not use it.
It is buggy ;. There is better one: 0. Already done!!! I've created independent command queues for Master and Slave devices. Now command reordering is performed separately for each device, thus, it is more efficient. The queue to be serviced for the next time is chosen according to special algorithm.
Currently it looks at queue size only, but I'm going to make something more clever in nearest future. INF file is added in Dist directory It is a little less buggy VIA -compatible chipset initialization code has been fixed. Now we handle the case of an unknown Revision Id properly.
Controller list initialization code has been fixed. There were a bug with NULL-pointers. I've implement 'human-friendly' ; algorithm of transfer rate slow-down when we have too high CRC Error-rate.
Now driver don't switch device to PIO mode immediately. It probes slower modes until suitable one is found. The mode is assumed to be suitable if it shows much better results. If such mode can be found the device is switched to use this mode permanently. This technology solves problem with cond. I would be thankful to everyone who takes it for testing and tell me where it works and where it doesn't.
The technology of working with controllers those have 2 channels available via single PCI device was dramatically changed. NT designers assumed that device can't interrupt until its previous interrupt is serviced. Thus, we can't programm one channel until transfer is completed on another channel. I've used a kind of workaround. New DeviceObject connected to the same interrupt is created.
It receives and queues interrupts from another channel. IO request queue sorting by LBA is implemented. I've also tried transfer rates for simple copy, but the results were unstable. The experiments with sorting algorithm will go on. DMA Engine is enabled and works now!!!
According to IDE BusMaster specification, the controller must automatically stitch to this mode after power on or reset. Device response wait timeout was changed from 5 to 0. Especially because it is possible and even recomended by Microsoft to avoid such waits. Replies Arrow down to Drives, then enter.
Then click ESC to save and exit. If you wish to use the Driver, you can find it here Bev. Post the issue in the appropriate Board, where they will be answered. Message Edited by shesagordie on PM. Sata Driver Nlite. Great stuff people.. I too wish that Vista had never been born, what a load of rubbish. Great site here, thanks again.. Wes S 2 Bronze. Being cautious I installed a second harddrive just to play with the installation.
My first attempt was to simply edit the boot sequence to boot from a CD. So I downloaded a lite version of Nero and burned another coaster. This time I got by the pci error but encounterd "ohci That got me here. But this got me back to the "pci. Examining the.
0コメント